1. Field of the Invention
The present invention relates to a method of manufacturing a metal oxide semiconductor (MOS) transistor, and more particularly to a method of manufacturing a metal oxide semiconductor transistor with a Y structure metal gate.
2. Description of the Prior Art
As semiconductor technology improves, 45 nm semiconductor devices are now being manufactured. Current metal-oxide-semiconductor field-effect transistors (MOSFETs) often utilize poly-silicon to make a gate. A doped poly-silicon gate has problems, however, such as a depletion effect of the poly-silicon gate, and boron penetrates through a channel.
Take the depletion effect of the poly-silicon gate as an example. When the poly-silicon gate is in an inversion, carrier depletion occurs between the poly-silicon gate and the gate dielectric layer. If this poly-silicon gate has the afore-mentioned depletion effect, the effect of the gate capacitance will decrease, but a high quality metal oxide semiconductor transistor should have a high gate capacitance. If the gate capacitance is high, more electric charge will accumulate in two sides of the gate capacitance. More electric charge therefore accumulates in the channel, so when the metal oxide semiconductor transistor has a bias voltage, the speed of the electric current between the source/drain will be improved.
Please refer to FIG. 1A. FIG. 1A is a schematic diagram, which illustrates the metal oxide semiconductor transistor having a depletion effect. A substrate 10 has a gate structure 12 thereof in FIG. 1A. A gate dielectric layer 15 is positioned between the gate structure 12 and the substrate 10. The source/drain 14 are in the two sides of the gate structure 12 in the substrate 10. Around the gate structure 12 is a spacer 16. The gate structure 12, the source/drain 14 form the metal oxide semiconductor transistor 18. The gate structure 12 is made from poly-silicon. When the metal oxide semiconductor transistor 18 has a depletion effect, carrier charges will accumulate between the gate structure 12 and the gate dielectric layer 15. Therefore, the thickness of the equivalent gate dielectric layer increases, while the gate capacitance decreases. The total capacitance decreases, and the drive effect of the metal oxide semiconductor transistor is reduced.
To avoid the above-mentioned depletion effect of the poly-silicon gate, the current industry utilizes a metal gate to replace the poly-silicon gate. A so-called replacement metal gate approach is processed with a dummy poly-silicon gate is formed first, and the dummy poly-silicon gate is then removed to form a recess. A metal gate is formed in the recess. Furthermore, a barrier layer and a High-k material layer are formed between the metal gate and the substrate to avoid the leakage of the gate structure and to increase the flexibility of the process. This structure is usually utilized in technology generation equal to or less than 45 nm to decrease the depletion effect of the poly-silicon. Since the source/drain 14 implantation and activation processes have been processed prior to the metal gate formation, the less thermal budget concern of the replacement metal gate could be achieved.
Before the metal fills the recess in the replacement gate process, a barrier layer must be deposited on the inner sidewalls of the recess. The depth/width (L/W) ratio of the recess is too high due to the narrow channel length, so the barrier layer is easy to form poor step coverage in the recess inner sidewall and would cause overhang effect on top of the recess as referred to FIG. 1B. The recess opening becomes smaller with the overhang formation, and the metal filling step is easy to form void in the recess as shown in FIG. 1C. The poor step coverage and the void formed after metal gate process would cause the issues such as the work function deviation and the chemical damage during planarity process. Therefore, to manufacture a metal oxide semiconductor transistor with no poor barrier layer step coverage is an important issue in the semiconductor industry.